Constant-load energy recovery memory for efficient high-speed operation

ABSTRACT

This paper proposes a constant-load SRAM design for highly efficient recovery of bit-line energy with a resonant power-clock supply. For each bit-line pair, the proposed SRAM includes a dummy bit-line of sufficient capacitance to ensure that the memory array presents a constant capacitive load to the power-clock, regardless of data or operation. Using a single-phase power-clock waveform, read and write operations are performed with single-cycle latency. The efficiency of the proposed SRAM has been assessed through simulations of 128x256 arrays with 0.25µm process parameters and a 42/58 write/non-write access pattern. Assuming lossless power-clock generation, the proposed SRAM dissipates 37% less power than its conventional counterpart at 400MHz/2.5V. When the overhead of power-clock generation is included, the proposed SRAM dissipates at least 27% less power than conventional SRAM.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Static memory (SRAM)

General Terms:
Design, Performance

Keywords:
adiabatic circuitry, cache memories, charge recovery, low-energy design, low-power computing, on-chip memories