Process variation and prerouting interconnect delay uncertainty affect timing and power for modern VLSI designs in nanometer technologies. This paper presents the first in-depth study on stochastic physical synthesis algorithms leveraging statistical ...

Keywords: algorithms, field-programmable gate arrays (FPGAs), timing, uncertainty

Modern FPGA chips contain multiple dedicated clocking networks, because nearly all real designs contain multiple clock domains. In this paper, we present an FPGA technology mapping algorithm targeting designs with multi-clock domains such as those containing ...

Keywords: co-processor, compute acceleration, high-performance computing, reconfigurable computing

In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a bicliquestar replacement technique. In hierarchical timing analysis, each functional block is characterized into an abstract timing model. The complexity ...

Keywords: biclique-star replacement, hierarchical timing analysis

Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address the verification ...

We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent false paths and multi-cycle paths. The complexity of the subgraph representation ...

Keywords: biclique covering, false subgraphs, multi-cycle subgraphs, static timing analysis, time shifting

We improve the efficiency of static timing analysis when false paths are considered. The efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. However, ...

Static timing analysis (STA) with multiple clock domains and complicated exception conditions is a complex practical problem that can dramatically increase compilation time, both for back-end analysis and during place and route. In FPGA placement, timing ...

Keywords: FPGA, cut-path, multicycle, placement, thru-x, timing analysis