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| 2009
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1
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A fault tolerant, area efficient architecture for Shor's factoring algorithm
Mark G. Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz
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June 2009
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ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture
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Publisher: ACM
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Full text available: |
 Pdf
(479.00 KB)
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| Bibliometrics: Downloads (6 Weeks): 52, Downloads (12 Months): 108, Citation Count: 0 |
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We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder circuits. Our custom ...
Keywords: cad, control, ion trap, layout, quantum computing
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Also published in: |
| June 2009 |
SIGARCH Computer Architecture News |
Volume 37 Issue 3 |
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| 2008
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2
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Running a Quantum Circuit at the Speed of Data
Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz
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June 2008
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ISCA '08: Proceedings of the 35th International Symposium on Computer Architecture
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Publisher: ACM
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Full text available: |
Pdf
(885.66 KB)
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| Bibliometrics: Downloads (6 Weeks): 36, Downloads (12 Months): 120, Citation Count: 1 |
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We analyze circuits for kernels from popular quantum computing applications, characterizing the hardware resources necessary to take ancilla preparation off the critical path. The result is a chip entirely dominated by ancilla generation circuits. To ...
Keywords: quantum, ancilla factory, microarchitecture
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Also published in: |
| June 2008 |
SIGARCH Computer Architecture News |
Volume 36 Issue 3 |
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| 2007
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3
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Automated generation of layout and control for quantum circuits
Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz
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May 2007
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CF '07: Proceedings of the 4th international conference on Computing frontiers
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Publisher: ACM
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Full text available: |
Pdf
(342.62 KB)
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| Bibliometrics: Downloads (6 Weeks): 5, Downloads (12 Months): 24, Citation Count: 2 |
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We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we investigate grid-based layouts and show a performance variance of four times ...
Keywords: CAD, control, ion trap, layout, quantum computing
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| 2006
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4
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Interconnection Networks for Scalable Quantum Computers
Nemanja Isailovic, Yatish Patel, Mark Whitney, John Kubiatowicz
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June 2006
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ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture
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Publisher: ACM
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Full text available: |
Pdf
(615.98 KB)
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| Bibliometrics: Downloads (6 Weeks): 34, Downloads (12 Months): 71, Citation Count: 5 |
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We show that the problem of communication in a quantum computer reduces to constructing reliable quantum channels by distributing high-fidelity EPR pairs. We develop analytical models of the latency, bandwidth, error rate and resource utilization of ...
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Also published in: |
| May 2006 |
SIGARCH Computer Architecture News |
Volume 34 Issue 2 |
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| 2004
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5
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Datapath and control for quantum wires
Nemanja Isailovic, Mark Whitney, Yatish Patel, John Kubiatowicz, Dean Copsey, Frederic T. Chong, Isaac L. Chuang, Mark Oskin
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March 2004
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Transactions on Architecture and Code Optimization (TACO)
, Volume 1 Issue 1
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Publisher: ACM
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Full text available: |
Pdf
(476.83 KB)
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| Bibliometrics: Downloads (6 Weeks): 10, Downloads (12 Months): 70, Citation Count: 3 |
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As quantum computing moves closer to reality the need for basic architectural studies becomes more pressing. Quantum wires, which transport quantum data, will be a fundamental component in all anticipated silicon quantum architectures. Since they cannot ...
Keywords: Architecture, Control, Layout
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6
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Exploiting Prediction to Reduce Power on Buses
Victor Wen, Mark Whitney, Yatish Patel, John D. Kubiatowicz
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February 2004
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HPCA '04: Proceedings of the 10th International Symposium on High Performance Computer Architecture
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Publisher: IEEE Computer Society
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| Bibliometrics: Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 3 |
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We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified SimpleScalar simulator and SPEC benchmarks. We show an average of 35% savings ...
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| 2003
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7
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Post-placement C-slow retiming for the xilinx virtex FPGA
Nicholas Weaver, Yury Markovskiy, Yatish Patel, John Wawrzynek
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February 2003
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FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
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Publisher: ACM
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Full text available: |
Pdf
(222.65 KB)
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| Bibliometrics: Downloads (6 Weeks): 2, Downloads (12 Months): 31, Citation Count: 1 |
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C-slow retiming is a process of automatically increasing the throughput of a design by enabling fine grained pipelining of problems with feedback loops. This transformation is especially appropriate when applied to FPGA designs because of the large number ...
Keywords: C-slow retiming, FPGA CAD, FPGA optimization, retiming
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| 2002
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8
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HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform
Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto Sangiovanni-Vincentelli
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May 2002
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CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign
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Publisher: ACM
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Full text available: |
Pdf
(575.30 KB)
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| Bibliometrics: Downloads (6 Weeks): 14, Downloads (12 Months): 71, Citation Count: 15 |
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This paper studies the use of a reconfigurable architecture platform for embedded control applications aimed at improving real time performance. The hw/sw codesign methodology from POLIS is used. It starts from high-level specifications, optimizes an ...
Keywords: CSoC, code generation, hw/sw co-design
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