Wireless Sensor Networks are a fast-growing class of systems. They offer many new design challenges, due to stringent requirements like tight energy budgets, low-cost components, limited processing resources, and small footprint devices. Such strict ...

Keywords: Reliability, data models, wireless sensor networks, error correction.

Manufacturing and operation-induced variations have emerged as a critical challenge in designing integrated circuits (ICs) under the nanometer technology regime. Most work on addressing variations has focused on device, circuit, and logic-level solutions. ...

Keywords: Integrated Circuits, Nanoscale, System-on-chip, variations, system-level design

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that ...

Keywords: communication architectures, high-performance communication, on-chip buses, system-on-chip (SoC)

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, ...

Keywords: CMOS digital circuit, robustness, single-event-upset (SEU), transient error

With the increased popularity of wireless broad-band networks and the growing demand for multimedia applications, such as streaming video and teleconferencing, there is a need to support diverse multimedia services over the wireless medium. In order ...

Keywords: IEEE 802.11e, quality of service, service level agreements, video streaming, wireless LAN

The power characteristics of System-on-chips (SoCs) in nanoscale technologies are significantly impacted by process variations, making it important to consider these effects during system-level power analysis and optimization. In this paper, we identify ...

Keywords: low power design, power management, process variations, system-on-chip

Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various design techniques to address process variations at the mask, circuit, and logic ...

Keywords: low power design, power analysis, power estimation, process variations, system-on-chip

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two circuit-level techniques to efficiently yet economically improve SEU tolerance ...

Dynamic variations in application functionality and performance requirements can lead to the imposition of widely disparate requirements on System-on-Chip (SoC) platform hardware over time. This has led to interest in the design and use of adaptive SoC ...

Soft-spot analysis identifies regions in a circuit that are most susceptible to multiple noise sources and their compound effects so that designers can harden those spots for greater robustness. HSpice simulation validates the methodology's quality, ...

Keywords: B.8.1 Reliability, Testing, and Fault-Tolerance, G.4.g Reliability and robustness, B.7 Integrated Circuits